mirror of https://github.com/meshcore-dev/MeshCore
1sthandy
20 hours ago
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GitHub
GitHub
10 changed files with 513 additions and 239 deletions
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#ifdef WITH_W5100S_POE |
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#include <Arduino.h> |
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#include <nrf.h> |
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#include "W5100SPoE.h" |
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// ── Early RST release (constructor priority 200) ─────────────────────────────
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// Runs before setup(), right after SystemInit — earlier than the ETHERNET_ENABLED
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// constructor in RAK4631Board.cpp that powers the peripheral rail (WB_IO2,
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// priority 102 runs first) but well before setup()/board.begin(), so the
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// W5100S starts drawing its full operating current as early as possible,
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// before the RAK19018 (Silvertel) converter's foldback timer expires.
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//
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// Raw registers because the Arduino GPIO layer isn't up this early.
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static void __attribute__((constructor(200))) w5100s_early_rst_release() { |
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// P0.21 = W5100S RST → HIGH (release from reset)
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NRF_P0->PIN_CNF[21] = |
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(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | |
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(GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) | |
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(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | |
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(GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) | |
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(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); |
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NRF_P0->OUTSET = (1UL << 21); |
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} |
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// ── Bit-banged SPI to the W5100S ────────────────────────────────────────────
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// Shares the SPI bus (SCK=3 / MOSI=30 / MISO=29) with the SX1262 radio; only
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// the chip-select differs (W5100S CS=26, SX1262 NSS=42). Bit-banged so it
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// works regardless of which SPIClass owns the bus and runs before RadioLib.
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// W5100S frame: write [0xF0][hi][lo][data], read [0x0F][hi][lo]->[data].
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#define ETH_SCK_PIN 3 |
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#define ETH_MOSI_PIN 30 |
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#define ETH_MISO_PIN 29 |
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#define LORA_NSS_PIN 42 |
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static void bb_write_reg(uint16_t addr, uint8_t data) { |
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const uint8_t frame[4] = { 0xF0, (uint8_t)(addr >> 8), (uint8_t)(addr & 0xFF), data }; |
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digitalWrite(W5100S_CS_PIN, LOW); |
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for (uint8_t b = 0; b < 4; b++) { |
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uint8_t v = frame[b]; |
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for (int8_t i = 7; i >= 0; i--) { |
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digitalWrite(ETH_MOSI_PIN, (v >> i) & 1); |
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digitalWrite(ETH_SCK_PIN, HIGH); |
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digitalWrite(ETH_SCK_PIN, LOW); |
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} |
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} |
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digitalWrite(W5100S_CS_PIN, HIGH); |
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} |
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static uint8_t bb_read_reg(uint16_t addr) { |
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const uint8_t frame[3] = { 0x0F, (uint8_t)(addr >> 8), (uint8_t)(addr & 0xFF) }; |
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digitalWrite(W5100S_CS_PIN, LOW); |
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for (uint8_t b = 0; b < 3; b++) { |
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uint8_t v = frame[b]; |
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for (int8_t i = 7; i >= 0; i--) { |
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digitalWrite(ETH_MOSI_PIN, (v >> i) & 1); |
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digitalWrite(ETH_SCK_PIN, HIGH); |
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digitalWrite(ETH_SCK_PIN, LOW); |
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} |
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} |
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uint8_t out = 0; |
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for (int8_t i = 7; i >= 0; i--) { |
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digitalWrite(ETH_SCK_PIN, HIGH); |
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out = (out << 1) | (digitalRead(ETH_MISO_PIN) & 1); |
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digitalWrite(ETH_SCK_PIN, LOW); |
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} |
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digitalWrite(W5100S_CS_PIN, HIGH); |
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return out; |
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} |
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// ── Full W5100S bring-up ────────────────────────────────────────────────────
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// Called from RAK4631Board::begin(). Confirms RST is driven (Arduino API, in
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// case the core re-init touched it), then soft-resets and reads VERSIONR.
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// Returns VERSIONR (0x51 = healthy W5100S).
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uint8_t w5100s_poe_init() { |
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delay(20); // let the rail/W5100S settle after the ETHERNET_ENABLED ctor's WB_IO2 enable
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// Park both chip-selects HIGH on the shared bus, RST released.
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pinMode(LORA_NSS_PIN, OUTPUT); digitalWrite(LORA_NSS_PIN, HIGH); |
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pinMode(W5100S_CS_PIN, OUTPUT); digitalWrite(W5100S_CS_PIN, HIGH); |
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pinMode(W5100S_RST_PIN, OUTPUT); digitalWrite(W5100S_RST_PIN, HIGH); |
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pinMode(ETH_SCK_PIN, OUTPUT); digitalWrite(ETH_SCK_PIN, LOW); |
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pinMode(ETH_MOSI_PIN, OUTPUT); digitalWrite(ETH_MOSI_PIN, LOW); |
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pinMode(ETH_MISO_PIN, INPUT); |
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bb_write_reg(0x0000, 0x80); // MR: software reset
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delay(2); |
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uint8_t ver = bb_read_reg(0x0080); // VERSIONR (0x51 on W5100S)
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// Chip stays powered and out of reset; PHY auto-negotiates with the switch
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// and the W5100S draws its full operating current.
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return ver; |
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} |
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#endif // WITH_W5100S_POE
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@ -0,0 +1,36 @@ |
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#pragma once |
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// W5100S early activation for PoE operation on RAK10720 (RAK4631 + RAK13800 +
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// RAK19018).
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//
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// ROOT CAUSE (confirmed via RAK forum + Meshtastic rak4631_eth_gw variant):
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// The RAK19018 PoE module (Silvertel Ag9905MT) enters a non-continuous
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// "gated pulse" mode when the load is below ~125-200 mA. A bare MeshCore
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// repeater draws only a few mA, so the converter never latches → the supply
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// pulses and the device never boots (fade-in / brighten / die / repeat LED).
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//
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// The fix: bring the W5100S PHY into its active state as early as possible.
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// An active W5100S draws ~120 mA — enough to keep the Silvertel converter
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// latched in continuous mode. The peripheral power rail (WB_IO2 / P1.02) is
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// already driven HIGH by an early constructor in RAK4631Board.cpp whenever
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// ETHERNET_ENABLED is set; this file only handles releasing RST (the rail
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// alone isn't enough — the chip must actually be brought out of reset and
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// made to draw its full current well before the Ethernet library's own
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// (later, disruptive) bring-up runs).
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//
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// Pin mapping (from Meshtastic rak4631_eth_gw variant.h):
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// RST → PIN_ETHERNET_RESET = 21 (P0.21 / WB_IO3)
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// CS → PIN_ETHERNET_SS = 26 (WB_SPI_CS)
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// SPI → SPI1 (SCK=3, MISO=29, MOSI=30) [not used in Layer 1]
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#ifndef W5100S_RST_PIN |
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#define W5100S_RST_PIN 21 // P0.21 / WB_IO3
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#endif |
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#ifndef W5100S_CS_PIN |
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#define W5100S_CS_PIN 26 // WB_SPI_CS
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#endif |
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// Called from RAK4631Board::begin(); fully brings up the W5100S (soft reset +
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// activation) so it draws full operating current. Returns VERSIONR (0x51 = ok).
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uint8_t w5100s_poe_init(); |
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